1. Technical Field
The present invention generally relates to computer memory subsystems, and more particularly to a Dynamic Random Access Memory (DRAM) subsystem. Still more particularly, the present invention relates to independent burst lengths for reads and writes in a DRAM subsystem.
2. Description of the Related Art
DRAM subsystems are well known in the art. A typical DRAM cell uses the gate capacitance of one or more field-effect transistors to provide the storage of a binary state. The charge on this capacitor will eventually leak and the DRAM cell may change state, causing an incorrect bit to be set or reset in memory. This problem is typically solved by a refresh scheme, which allows the gate of the field-effect transistors to be recharged according to the value stored in the cell, before sufficient discharge has occurred to cause an error.
In a typical DRAM memory system, one processor usually has control of the memory at a given time. Address lines and data lines are driven by the processor or buffers attached to the processor address and data signals.
The typical DRAM is formed by thousands of individual memory cells arranged in a matrix-like configuration. Each DRAM cell includes a capacitor which is electrically charged or discharged in a xe2x80x9cwritexe2x80x9d operation. The charge establishes a voltage on the capacitor, and the level of the voltage represents a data bit. The data bit represented by the capacitor charge is determined by comparing the capacitor voltage to a threshold reference.
The memory cells of the DRAM matrix are addressed by signals supplied on word lines and bit lines. The word lines extend in a horizontal reference direction in the matrix and connect to the memory cells in the horizontal rows and thus intersect vertical columns of memory cells in the matrix. The bit lines extend in a vertical reference direction in the matrix and connect to the memory cells in vertical columns and thus intersect horizontal rows of cells. By energizing a selected word line, the voltage from the memory cells in the horizontal row corresponding to the selected word line are presented on the bit lines extending from each of the cells.
The DRAM memory array is usually divided into one or more segments, and each of the segments is further divided into bit blocks. Each bit block has a plurality of memory cells, and those memory cells are organized into rows and columns in a matrix. Individual words are selected by addressing the DRAM segments, selecting individual columns in the bit blocks, and selecting the desired word line.
A read or write instruction consists of an address that references a particular address space in memory. Typically, a read and a write address has a default number of beats that is read or written. In standard systems the number of beats is dependent on the architecture of the DRAM and is programmed into the system operation procedures. The number is typically programmed at power-on during system initialization and is a static value (i.e., unchangeable once initially programmed at power-on).
Data is stored in DRAM arrays in beats. A DRAM memory array that provides 128 bytes of data per line may have 8 beats of data that are 16 bytes wide. Thus, for example, if the data bus is 16 bytes wide and each read request reads 128 bytes of data from within the DRAM array, then the DRAM array provides 8 beats of data in response to the read request.
In a standard memory access operation, data is read from memory, modified by the processor, and re-written to memory. Current DRAM operations requires that the number of beats of data written back to memory must be the same as the number of beats previously read, irrespective of the number of beats that is actually modified. For example, if the read request reads a 512 byte cache line having 8 beats that are each 64 bytes in width and a subsequent process modified data in only one portion of the line, e.g., 128 bytes, then the memory must still write all 512 bytes of data.
The current DRAM systems require all 512 bytes be re-written. As processor caches become larger, more sectoring will occur to help keep directory sizes small. This will result in longer read requests to improve the efficiency of the memory subsystems. These longer read requests conflict with the shorter write requests that result from modified sectors of the caches or from the I/O data transfers. The requirement that all writes to memory be the same length as the read operations to memory will result in a loss of bandwidth due to both the writing of unmodified data and the extra read requests that may be necessary when the full length of the write data is not available (i.e., read modified write operations). Statistically, there are more reads than writes to DRAM systems during operation, and where it is generally a good practice to speculatively read the un-accessed sectors of a sectored cache, it is not an efficient use of the memory bandwidth to write back all the unmodified sectors of the cache.
In some DRAM system designs, burst write procedures are available. A burst write procedure utilizes a mask bit that, when turned on, allows the system to not write data that is being transferred for a particular number of cycles. This permits a smaller number of data to be written to the memory array than was initially read and is being transferred by the write operation. However, with burst write, although the write operation is turned off, the space on the bus is still being utilized to transmit all the data and the various memory pins have to be run at the same rate as if all the data was being re-written. Burst write procedures therefore do not assist in the efficient utilization of the system bus.
Given the time loss inherent in writing entire lines of data when only some of the data cells have been changed, the present invention recognized that it would be desirable to have write bursts of a DRAM be a different sized (i.e., smaller) from the read bursts. A method by which only that part of a memory array line that is modified is written back to memory is a welcomed improvement. These and other benefits are provided in the present invention.
A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem is described. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory.
In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.
The invention finds applicability in high-performance servers, that have lots of sequential reads with small burst writes. The invention is also applicable to out-of-order high frequency central processing units (CPUs) that operate with a lot of speculation.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.